This invention relates generally to logic circuits, and more specifically to a type of transistor-transistor logic (TTL) buffer circuit having improved performance during output voltage transitions.
It has been recognized that TTL components are generally susceptible to power supply spikes or "bounce" during transitions in output voltage from one state to another. This problem is most detrimental when all of the TTL outputs make the same transition (i.e. from low to high, or from high to low). These power-supply spikes result from the relatively rapid rate of change of the current flowing through the inherent inductance in the power supply conductors within an IC package. As TTL integrated circuits have become faster, output transition times have decreased and this has resulted in increased power supply bounce due to the rapid turn-on of the output transistors.
Previous attempts to control power supply bounce have focussed on the technique of obtaining a controlled voltage ramp at the TTL circuit output. This approach is less than optimum in achieving the desired result, however, since the output current is proportional to the rate of change of the output voltage, and thus still changes very rapidly from zero to a finite value. The result is a large transient rate of change of current, and thus a substantial power supply bounce.
One example of a prior-art circuit in which power-supply bounce is partially controlled by providing a controlled voltage ramp at the output is shown in commonly-owned U.S. patent application Ser. No. 134,494, incorporated herein by reference. A background discussion of the power-supply bounce problem and earlier prior-art attempts to minimize this problem are detailed in that application. Another prior art circuit, employing MOS transistors in a configuration which partially controls power-supply bounce using a control signal with a square-root characteristic, is shown in European Patent Application No. EP-A-0 250 036.
An example of a substantially different circuit for controlling the rate of change of an output current in an FET circuit is shown in "IBM Technical Disclosure Bulletin", Vol. 27, No. 1A, June, l984, at pages 13-14, while a logic circuit incorporating transistors in a Darlington configuration for lowering the base potential of a transistor to limit changes in the transition time of an output voltage is shown in Japanese Kokai No. 61-170127.
Ideally, it would be desirable to have the output current (rather than voltage) increase linearly with time so that the power supply bounce stays at a relatively low and constant level during the transition. This would result in a parabolic voltage output waveform during the major portion of the transition period. Additionally, it would be desirable to reduce the power supply bounce without greatly increasing the propagation delay time or affecting the steady-state operation of the circuit.